1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a bottom to electrode of a capacitor in dynamic random access memory (DRAM).
2. Description of the Related Art
As the function of a microprocessor becomes more powerful, the program and calculation of software becomes more complicated, and thus the need for Dynamic Random Access Memory (DRAM) storage memory is increased. As the number of semiconductor devices incorporated in an integrated circuit increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is widely used. FIG. 1 is a circuit diagram of a DRAM memory cell. A capacitor C selected from an array of capacitors is used to store information as binary data by charging/discharging the capacitor C. Normally, a binary bit is stored in each capacitor, and when the capacitor C is free of charge, logic "0" is represented, whereas when the capacitor is fully charged, logic "1" is represented. In general, a dielectric film 101 is deposited between a top electrode (cell electrode) 102 and a bottom electrode (storage electrode) 100. The capacitor C is electrically coupled with a bit line BL. The read/write operation of the DRAM memory cell is performed by charging/discharging the capacitor C. The bit line BL is connected to the drain of a transfer field effect transistor T. The capacitor C is connected to the source of the transfer field effect transistor T. A signal is transmitted through a gate of the transfer field effect transistor T, which is used to control the capacitor C by turning on or off the connection with the bit line BL. In other words, the transfer field effect transistor T acts as a switch to control the charging and discharging of the capacitor C.
In a traditional DRAM, 2-dimensional capacitors called planar type capacitors are mainly used to store data. However, the planar type capacitors are not suitable for Therefore, a highly integrated DRAM needs 3-dimensional capacitors, such as stacked-type capacitors or trench type capacitors, to achieve the required performance level.
Compared to the planar type capacitors, the stacked-type capacitors or the trench-type capacitors can obtain a great amount of capacitance. However, the simple 3-dimensional capacitor is no longer adapted when a much more highly integrated DRAM is introduced.
Due to the requirement of continuously increasing integration, the memory cells of DRAM need to be further shrunk. It is well known by those skilled in the art that the more the memory cells shrink, the less the capacitance thereof will be. This causes the probability of a soft error created by the incidence of a .alpha. ray to increase. Therefore, a structure and a method of forming a capacitor having a desired capacitance even though the capacitor is further reduced in size, is urgently required.